Metal films have been utilized in semiconductor manufacturing to electrically connect together various components formed on a semiconductor wafer. For instance, vias, interconnects, trenches are just a few examples of such applications. Elemental aluminum and its alloys such as aluminum-copper have been used traditionally for these applications. The advantages of using aluminum and its alloys include the low resistivity, the superior adhesion to SiO2, the ease of patterning, the high purity and low cost of the materials.
Aluminum and aluminum alloys are not without drawbacks when utilized in semiconductor technology. Two of these drawbacks are the softness of the materials which results in difficulty in polishing and the electromigration phenomenon which results in circuit failure. For instance, the polishing problem has been observed in a process where metal films or metal conductive lines are formed in a damascene process by first filling troughs previously etched in an insulator with a metal and then polishing away metal deposited between the troughs. When a soft metal is used, i.e., aluminum, copper or aluminum-copper alloy, the surface of the metal lines may become scratched in a polishing process. The formation of defects during polishing of scratches, pockets, depressions or erosions in the metal surface significantly increases the line resistance and thus reduces the yield of the semiconductor manufacturing process.
In order to avoid these defects produced in the polishing process of soft metals, capping by hard layers has been tried by others to improve the wear resistance of the surface layer of the metal. However, this is achieved at the expense of higher capacitance as the line thickness increases. It is inherently difficult to improve the wear resistance of soft metals which requires the processing steps of polishing. Poor polishing results in variations in the line or via resistance.
It is therefore an object of the present invention to provide a soft metal conductor that has improved wear resistance in its uppermost surface and a method of making the same without the shortcomings of the prior art conductors and the prior art methods.
It is another object of the present invention to provide a soft metal conductor that has improved wear resistance in its uppermost surface such that a substantially scratch-free surface can be obtained after polishing in a chemical mechanical polishing process.
It is a further object of the present invention to provide a soft metal conductor that has improved wear resistance in its uppermost surface by simply modifying the processing conditions of the deposition process for the soft metal.
It is yet another object of the present invention to provide a soft metal conductor that has a substantially scratch-free surface upon polishing by depositing a soft metal layer consisting of metal grains having large grain sizes in its uppermost layer.
It is another further object of the present invention to provide an electrically conducting soft metal structure that has a substantially scratch-free surface upon polishing by depositing in the uppermost layer of said structure grains of soft metal not smaller than about 200 nm.
It is still another object of the present invention to provide an electrically conducting soft metal structure that has a substantially scratch-free surface upon polishing for use in a semiconductor device by depositing in the uppermost layer of said structure metal grains having grain sizes not smaller than about 20% of the thickness of the soft metal structure.
It is still another further object of the present invention to provide an electrically conducting soft metal structure that has a substantially scratch-free surface upon polishing for use in a semiconductor device wherein the surface has a layer of at least about 100 nm in thickness of large grain size metal grains deposited therein.
It is yet another further object of the present invention to provide a method of making a soft meal conductor that has a substantially scratch-free surface upon polishing for use in a semiconductor device by a physical vapor deposition technique, a chemical vapor deposition technique or a dual-step deposition technique.